The present invention relates to computer readable memory, and more particularly a sensing scheme for content addressable memory.
Content addressable memory (CAM) provides a hardware solution to the rapid search operations utilized in information networks, such as the internet. Unlike random access memory (RAM), which retrieves data from different locations in memory by a supplied address, CAMs search the entire memory for a supplied data word and return the address and possibly associated data. This design offers a faster method for matching functions, such as those performed by routers and network servers.
In order to rapidly compare a supplied data word with all stored data words in parallel, each CAM cell contains additional bit-comparison circuitry, aside from the storage element hardware. The additional hardware is coupled across each stored word with a match line. This arrangement allows all bits within a stored word to be compared in one clock cycle.
However, as advancements in memory technology allow for scaling of smaller devices, the margin between match and mismatch voltage signals becomes smaller. Such noise and random device variation increasingly provide timing and data retrieval uncertainty. Since CAM search hardware compares multiple bits in one line, the sensitivity to noise and variation is further increased.